Modelling, synthesis and rapid prototyping with the verilog HDL using active simulation
Ciletti, Michael D
Modelling, synthesis and rapid prototyping with the verilog HDL using active simulation - New Jersey Prentice Hall 1999 - xxii, 727p. : ill.
CDBK1574, CDBK1575- SET 1; CDBK1418,CDBK 1417-SET 2. Includes index.
139773983
Computer science
Hardware modelling -- Verilog
Logic system
Simulation -- Verilog
Verilog designs
Verilog Hardware Description Language
Verilog models
VHDL
Modelling, synthesis and rapid prototyping with the verilog HDL using active simulation - New Jersey Prentice Hall 1999 - xxii, 727p. : ill.
CDBK1574, CDBK1575- SET 1; CDBK1418,CDBK 1417-SET 2. Includes index.
139773983
Computer science
Hardware modelling -- Verilog
Logic system
Simulation -- Verilog
Verilog designs
Verilog Hardware Description Language
Verilog models
VHDL