Ciletti, Michael D <br/><br/>
Modelling, synthesis and rapid prototyping with the verilog HDL  using active simulation 

 - New Jersey  Prentice Hall  1999 
 - xxii, 727p. : ill.  
<br/><br/> CDBK1574, CDBK1575- SET 1; CDBK1418,CDBK 1417-SET 2. Includes index. 
<br/><br/><label>ISBN: </label>139773983 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Computer science<br/>Hardware modelling -- Verilog<br/>Logic system<br/>Simulation -- Verilog<br/>Verilog designs<br/>Verilog Hardware Description Language<br/>Verilog models<br/>VHDL