TY  - BOOK
AU  - Prashant Saxena
AU  - Rupesh S Shelar
AU  - Sschin S Sapatnekar
TI  - Routing congestion in VLSI circuits : estimation and optimization
T2  - Series on integrated circuits and systems
SN  - 9788184893885
PB  - New Delhi
KW  - Routing congestion  VLSI Circuits
KW  - VLSI Circuits
KW  - VLSI Design flow
N1  - Includes bibliographical references and index
ER  -